What's the difference between Chisel and Lava and CLaSH?

I've been studying the sources of Chisel and also various Lavas (Kansas, Chalmers and Xilinx flavors) and CLaSH. I'm trying to understand what's the main selling points of Chisel versus the...

How to generate an asynchronous reset verilog always blocks with chisel

Chisel generate always blocks with only clock in sensivity list : always @posedge(clk) begin [...] end Is it possible to configure Module to use an asynchronous reset and generate an always...

Is there a simple example of how to generate verilog from Chisel3 module?

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog. I take Gcd source code given on official web page of chisel. import chisel3._ class GCD extends Module { val...

Simplest way to generate Verilog code from Chisel code

What is the simplest way to generate Verilog code from existing Chisel code? Would i have to create my own build file? For example from a standalone scala file (AND.scala) like the following...

Learning Chisel -- advanced examples to understand Rocket Chip code

The Berkeley implementation of RISC-V is called Rocket Chip and it is written in a hardware language called Chisel. Chisel is object oriented, and it has been difficult for the people on our team...

What is Clone in Chisel

I am a new learner of Chisel. What is the purpose of Cloning in Chisel? I saw somewhere written, "it creates a shallow copy". Why do we need it? Here are examples. Could you please elaborate...

Formal verification with Chisel

Is it possible to do formal verification with Chisel3 HDL language? If yes, is there an open-source software to do that ? I know that we can do verilog formal verification with Yosys, but with chisel ?

How to ceil the result for UInt division in Chisel

As the title stated, how to do that? val a = 3.U val result = a / 2.U result would be 1.U However I want to apply ceil on division. val result = ceil(a / 2.U ) Therefore, I could get 2.U of...

Chisel/Firrtl Verilog backend proof of work

Is there some built in test or tools for formal verification of chisel or firrtl design vs generated verilog? On which concepts verilog backend is build? Is there any bugs in it?

How to convert Vec(n,Bool()) into UInt value

As title, I want to covert Vec(Bool()) into UInt value. For example class MyModule extends Module { val io = IO(new Bundle { val in_data = Input (Vec (3, Bool() ) val result =...

React JS state that references other state property

I want to have a component with a list of products and a list of listItems which renders each product, but it is giving me the error: TypeError: Cannot read property 'products' of undefined new...

Dual port memories

I've managed to get Chisel to use a hard memory macro with the correct usage of a SeqMem() instance, but they're for single port memories only. Is there a way to get Chisel to infer a dual port...

Rebased and now facing Scala dependency issues

I'm not quite sure where I was with the rocket-chip repo before the rebase, but it was prior to the changeover to using Scala 2.12.4 (previously I was at 2.11.12). I've rebased, sorted out...

How to synthesis Rocket-Chip on Vivado?

I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I...

How to import getVerilog() function from the bootcamp examples?

I am not sure I understand how to use the getVerilog function from: https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb [error] passthrough_test.scala:18:11: not...

How to keep all variable name In chisel when generate Verilog code

The Register name in chisel can be definitly found in verilog ,. but Wire name sometimes ellipsis in verilog code. for example , I cant find sjwr ,sjwaddr name in verilog . val sjwr =...

Simulating a CPU design written in Chisel

I've written a single-cycled CPU in Chisel3 which implements most of the RV32I instructions (except CSR, Fence, ECALL/BREAK, LB/SB, which may be included later). The instructions are currently...

How can I find some manuals about rocket-chip?

I'm learning the code of rocket-chip. But I find it difficult to read its code due to the complex relationship. So I need some maunal to help me. Unluckily, it seems that there are few manuals...

How to extract a standalone FPU module from Rocket-Chip Chisel code?

I am working on Rocket Chip Generator, which is a SoC written in Chisel. My objective is to extract the Floating-Point Unit, in order to synthesize it and study its power consumption/area ...etc....

Set-associative TLB on Rocket Chip

I am trying to address if Rocket Chip Generator supports a set-associative TLB (both for L1 and L2 TLB) but I cannot find any straightforward code about that in RocketCore.scala or PTW.scala. On...

Error: Attempted to instantiate a Module without wrapping it in Module()

Top module is as follows; class PE (DataWidth: Int, NumLinks: Int, NumEntries: Int, FifoDepth: Int) extends Module { val io = IO(new Bundle { ... }) ... } I think that this is...

Error "Makefrag-verilator:20: recipe for target" while running "make" in VCS, Emulator Vsim directories

I am working on building the Rocket-Chip on my Ubuntu 18.04. I have already built the RISC-V toolchain, RISC-V Tools, Rocket-Tools, Vertilator, Sbt on my machine. I am following the guidelines...

chisel partial bulk connection with "<>" operator

I'm having trouble to do partial bulk connection with <>. I saw in the book Digital Design with Chisel (4.3 Bulk Connections). It is allowed to connect two bundles with partially matched...

Is there an accepted way to get a Gray Code counter in Chisel?

I'm looking to write counters in Chisel3 that will be used to address subunits. If the counter matches some register in a subunit then the subunit fires, otherwise it doesn't. I would much rather...

How to create a array/vec of Chisel modules

I created a CHISEL Class (extends) module called SaturatingCounter (code below in case it is relevant). I want an array/Seq of these counters in another module. EDIT: I found this answer. But when...

Finding Neighboring Pixels [Python]

Please bear with me as this is my first post after a long-time (unregistered) user of the site. I have an image file where there are specific regions in the image of interest. These regions have...

Why does sbt fail with "Expected ';'"?

When I run example chisel design from the learning-journey project, I am seeing error as following: $ ./run-examples.sh SimpleALU ... [info] Set current project to chisel-tutorial (in...

What FPGA vendor boards are supported (well) by Chisel?

What FPGA vendor boards are supported (well) by Chisel? Are most FPGAs on the market generically supported? Or do we need to be careful about some details when buying? If so, what should we pay...

Get an item in Seq using UInt

I'm trying to write a cache memory, so I created a Seq of type Mem because I'm trying to have access to all elements in a set of the cache at the same time. val metaMem = Seq.fill(nWays)...

Dumping memory in a VCD file

My main problem is that I can't have access to my inner signals while I'm using peek/poke testing. For example, I'm trying to debug a cache design and because of that, I want to see the content of...